Integrated semiconductor memory circuits, particularly those employing cells which include essentially a single switch or transistor and a storage capacitor have achieved high memory cell densities. One of the simplest circuits for providing small memory cells, which are now conventional, is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967 by R. H. Dennard. Each of these cells employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line. In also commonly assigned U.S. Pat. Nos. 3,811,076 by W. M. Smith and 3,841,926 by R. H. Garnache and W. M. Smith, both filed Jan. 2, 1973, there is disclosed a one device field effect transistor memory cell of the type described in the above-identified Dennard patent which is made to a small size by utilizing a layer of doped polysilicon and an N+ diffusion region in a P-type semiconductor substrate separated by a dielectric medium disposed on the surface of a semiconductor substrate for forming a storage capacitor. The polysilicon layer is connected to a source of fixed or bias potential and the N+ diffusion region receives a quantity of charge dependent upon the voltage applied to a bit/sense line through a field effect transistor.
To further reduce the size of memory cells, commonly assigned U.S. patent application Ser. No. 036,722 filed by I. T. Ho and J. Riseman on May 7, 1979 and IBM Technical Disclosure Bulletin, Vol. 21, No. 6 November 1978, pp. 2329-2330, by I. T. Ho, J. Riseman and H. N. Yu disclose memories having a V- or U-groove with source and drain diffusions disposed at the surface of the substrate, with inversion storage, and U.S. Pat. No. 4,105,475, filed Oct. 1, 1976, discloses a one device memory cell having a V-groove below which is disposed a buried storage node, with a bit line diffusion at the surface of the substrate.
Commonly assigned U.S. Pat. No. 3,986,180, filed by P. E. Cade on Sept. 22, 1975, teaches a memory system utilizing a junction field effect transistor (JFET) wherein the storage capacitor is formed between a word line and a channel region. U.S. Pat. No. 3,971,055, filed Aug. 21, 1974, discloses an analog memory circuit employing a JFET wherein the channel between the source and drain is controlled by a depletion layer produced by the stored charge in a PN junction, and U.S. Pat. No. 4,161,741, filed July 11, 1977, also discloses a JFET memory wherein information stored at a floating gate between two main electrode regions is read out non-destructively.
In U.S. Pat. No. 4,163,985, filed Sept. 30, 1977, there is disclosed a non-volatile memory cell that has a buried N+ layer from which charge is injected into the insulator of an N channel metal nitride oxide semiconductor type device.
In an article entitled "Multilevel Random-Access Memory Using One Transistor Per Cell" by R. A. Heald and D. A. Hodges, IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, August 1976, pp. 519-528, there is disclosed a multilevel non-destructive read out memory cell using a JFET with a surface gate and a buried floating gate controlling the resistance of the channel which extends between source and drain diffusions located at the surface of the substrate.